This application claims priority from Indian patent application No. 1040/Del/2001, filed Oct. 10, 2002; and is herein incorporated by reference.
The present invention relates to an improved multistage binary hierarchy decoder for large number of outputs using smaller size decoders and a pass gate matrix.
FIG. 1 shows an example of a 2xc3x974 decoder with active low outputs. The decoder has two inputs (1.1) and (1.2) and 4 outputs (1.3) to (1.6). FIG. 2 defines another implementation of 2xc3x974 decoder, which has active high outputs. The 2 inputs are (2.1) and (2.2) while the outputs are (2.3) to (2.6). These decoders are examples of flat decoders. However, this approach is not suitable for larger decoders, as it requires substantial hardware. In such cases multi-stage decoders are used to reduce the hardware required. As an example, a 4xc3x9716 decoder can be made using two 2xc3x974 decoders. There are several schemes for two stage decoding. One such scheme is shown in FIG. 3. Here two decoders of the type shown in FIG. 1 are used as a first stage of the decoder with inputs (3.1) and (3.2) for the first decoder and inputs (3.3) and (3.4) for the second decoder. In the second stage of the decoder each output from each 2xc3x974 decoder is NORed with each corresponding output of the second 2xc3x974 decoder forming a 4xc3x9716 decoder with outputs OUT0 through OUT15. This decoder provides active high outputs.
For making a decoder with active low outputs, the decoder of FIG. 2 can be used as the first stage of the decoder and in the second stage each output of the first 2xc3x974 decoder will be NANDed with each corresponding output of the second 2xc3x974 decoder to form the 4xc3x9716 decoder. Even such two stage decoder schemes consume a lot of hardware and are hence not suitable for making very large size decoders.
Accordingly, one embodiment of the present invention provides an apparatus and method for overcoming the above drawbacks for making large size decoders by using a binary hierarchy of smaller size decoders together with a pass gate matrix.
This embodiment is an improved multi-stage binary hierarchy decoder characterized in that at least one of the decoding stages subsequent to the first stage is implemented as a Transmission Gate Matrix (TGM) in which a single transmission gate enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit.
The TGM is an arrangement of transmission gates in row and column form with the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage, while the inputs of all transmission gates in the same row are connected together to a single output of the second decoder from the previous stage.
A discharge matrix is included at the output of the TGM for the case when the outputs are active high in order to pull inactive outputs low, while a charge matrix is included at the output of the TGM for the case of active low outputs in order to pull inactive outputs high.
The discharge matrix is an arrangement of grouped NMOS transistors having source terminals connected to ground, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in the TGM and each drain connected to an output from the TGM.
The charge matrix is an arrangement of grouped PMOS transistors having source terminals connected to the positive supply terminal, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in the TGM, and each drain connected to an output from the TGM.